Engineering 25 Lab 3

Building Two Simple Parallel CPUs

Aron Dobos, Alexey Rostapshov
Professor Bruce Maxwell
Computer Architecture
March 29, 2004

The purpose of this laboratory was to design a simple CPU modeled on a simplified Von Neumann's IAS computer. The CPU was implemented using the dataflow architecture programmed in VHDL. A digital state machine of the CPU, including the fetch-decode-execute cycle was first developed. This state machine was then coded into VHDL. As a significant extension of these principles, a secondary CPU was also designed in order to provide the capability to execute instructions in parallel. Each CPU was then implemented on an Altera FPGA board. The two boards used the EPP Parallel protocol in order to communicate.

The Basic SSC Architecture  -   The architecture of the SSC (Simple Swarthmore Computer) is a simplified version of the standard Harvard architecture. The SSC has separate data (RAM) and program (ROM) memories, and a few internal registers for data manipulation and control. The internal register organization closely follows that of Von Neumann IAS computer, and a brief outline follows:

Accumulator (ACC) - All ALU operations are between the value in the accumulator and a memory based operand. The result of the ALU operation is put back in the accumulator.
• Multiplier/Quotient (MQ) - The MQ register serves as a 1 byte stack for holding temporary values inside the processor. If multiplication and division instructions were implemented, this register would serve to hold the upper byte of the multiplication, or the remainder of the division perhaps.
• Flags - The flags register is modified based on the results of ALU operations. The SSC has flags for ALU overflow and carry.
• Program Counter (PC) - The program counter holds the program memory address of the currently executing instruction and is advanced to the next instruction address after each instruction has finished executing. Conditional jumps can cause programs to advance to a non-consecutive instruction, but usually the PC is simply incremented to the next program memory address.
• Instruction Register (IR) - The instruction register holds the current 10-bit instruction that specifies the current operation and operands/addresses.

The simple instruction set allows for basic arithmetic operations and control. Each instruction has a few bits of opcode that specify the operation to be executed, as well as an immediate operand value or a memory address reference to an operand. Some instructions take no address or operands. The instructions supported can be grouped into the following four categories.

A full listing of the instruction set with the machine instructions along with with the assembly code mnemonics is given below.

Parallel Extensions to the Core SSC Implementation - The parallel extensions to the SSC required modifications to the original STORIO and LOADIO commands listed above in the original instruction set. The store (outb) command now uses the lower 5 bits of the instruction to specify either to output data to the hexadecimal 7-segment LED displays (all 0's), or to write to one of 8 buffers to send to the second parallel CPU. A pattern of all 1's causes the data to be sent to the second CPU. The load (inb) instruction was modified similarly. All 0's retrives a byte from the dipswitches on the primary CPU's Altera board. All 1's waits for data arrive from the second CPU. An outline is reproduced below:

Opcode
Lower 5 bits
Asm
 Description
01000
00000
outb
Write to the LEDs directly
01000
01xxx
outbpb [0-7]
Write to one of 8 (xxx) data buffers
01000
11111
sdpcpu 
Send data to CPU2 over the parallel bus
01001
00000
inb
Read directly from the dipswitches on the primary Altera board
01001
11111
wdpcpu
Wait for data to arrive to the I/O device from CPU2 over the bus

For simplicity, the secondary processing unit handled mostly everything within a single I/O component. A 64 bit RAM module was the only other element integrated into the secondary unit. The implementation of the I/O module is explained more specifically in a later section.

The second CPU uses an instruction set different from the primary processor. There were several reasons for making a separate 8-bit instruction set. First, in our case the second CPU would perform fewer functions than the primary CPU. A smaller instruction set also made communication between the two units easier to implement since the I/O units were connected by an 8-bit bus. Finally, since both the eight bit data and instructions were received into the same registers, and eight bit instruction set made sense.

Only the instructions that were used for testing the CPU were created. However, since this is a proof-of-concept design it would be trivial to expand the instruction set. The groupings of the instructions implemented, along with their descriptions, are shown below in Tables *** and ***. These instructions were used to obtain two numbers from the dip switches, average them, and send them back to the primary CPU. Two different "priming" functions were required to get numbers from the dipswitches since, due to poorly debounced buttons, it would be impossible to record two different numbers in quick succession.

The diagram that follows shows the possible states that the primary (controlling) SSC might be in. The very original SSC implementation had a much larger number of states, but to optimize the execution to take fewer clock cycles per instruction, nearly all redundant states were removed, leaving the following state diagram.

Discussion of Execution Stages - To execute an add instruction, we can simply follow the above state diagram.

• S_Init : This state simply sets the values of all registers to 0, and proceeds to the Fetch0 state.
• S_Fetch0 : This state applies the program counter (PC) value to the program memory's address lines, and moves to the Fetch1 state.
• S_Fetch1 : The instruction is now available on the program memory data lines, and is loaded into the instruction register (IR). The next state is the Decode0 state.
• S_Decode0 : This state determines that the instruction is an ADD instruction, and applies the lower five bits of the instruction register (the operand address) to the data memory address lines. The next state is the Exec_ADD_0 state.
• S_Exec_ADD_0 : This state adds the value on the data memory lines to the value of the accumulator, setting any flags in the process, and continues to the S_ExecDone state.
• S_Exec_Done : This state increments the program counter and returns to the Fetch0 state.

To execute an unconditional jump instruction, we again follow the state diagram, ignoring this time the S_Init0 state.

• S_Fetch0 : The program counter (PC) is applied to the program memory's address lines, and moves to the Fetch1 state.
• S_Fetch1 : The instruction is now available on the program memory data lines, and is loaded into the instruction register (IR). The next state is the Decode0 state.
• S_Decode0 : This state determines that the instruction is an unconditional JUMP ( j xxxxx ) instruction, and copies the lower five bits of the IR to the PC, before returning to the Fetch0 state. This way, the Fetch0 state will pull in the next instruction from the address specified in the jump instruction.

This state machine diagram is the state machine description for the aforedescribed secondary parallel SSC.

The data and program memory modules were implemented using the built-in Altera megafunctions lpm_ram and lpm_rom, respectively. The data memory holds 32 8-bit values, and thus requires 5 bits of addressing. The program memory also holds 32 instructions, but each is 10 bits wide. In order to avoid problems with sychronizing memory accesses, the memories were unclocked and thus functioned asynchronously. It was assumed that after applying an address, the memory value would be available on the data lines on the following clock cycle.

The I/O device connected to the primary CPU had multiple functions. The CPU uses two commands for interfacing with the I/O module. These are the STORIO and LOADIO operations, as described in Table *** on page ***. These functions have to specify the port they are accessing. For the STOREIO command, this allows the CPU to either write to the seven segment displays or to one of the eight buffers used in sending data to the second CPU unit. After the CPU dumps up to 8 bytes of data to the I/O buffers, an access to port "11111" signals the I/O device to send the buffered data to the secondary I/O device.

For loading the data from the I/O device, the CPU either accesses the dip switches or the cached byte sent from the secondary device. The latter operation requires the CPU to wait for a signal from the I/O device indicating it had received the requested data.

In order for the two I/O devices to communicate, the EPP parallel protocol was used over a bus connecting the two boards. The protocol had to be bidirectional since there were not enough pins connecting the two devices to allow for dedicated single directional lines. The bidirectional requirement severely complicated the programming of the protocol since tri-state buffers with feedback had to be implemented. The buffers were internal to the I/O device and their implementation is described later in the VHDL section. In addition, the protocol was modified by adding a clock signal from the primary CPU to the secondary device in order to assure synchronization. Moreover, this clock had to be slowed down in order to allow full propagation of the assorted signals from one board to another. The diagram and the bus pins used in employing the bi-directional communication protocol are shown in Diagram *** and Table *** below.

The secondary I/O device contains the processing unit, so it serves the purpose of both receiving and decoding the instructions. The I/O device is connected to the primary CPU using a parallel data cable and uses the EPP parallel protocol, as described above.

As the data is received into the internal registers of the I/O module, it is immediately written to the 8x8 bit RAM. The lpm_ram function is used to implement the memory storage. Once the data transfer is complete, the I/O component moves into the CPU mode and fetches, decodes, and executes the instructions. Both the instructions and the data are stored in the RAM, so care has to be taken not to clobber needed data or instructions. In this version, there are no jump bits so the program counter is simply incremented after every operation.

When the instruction to send data back to the primary CPU is executed, the I/O device sends an interrupt back to the main device as long as no writing operation is occurring. It then places the data stored in the address specified by the SENDIO function on the bus.

• ssc_core.vhd - The basic optimized SSC processor core.
• ssc_core_original.vhd - SSC processor core without optimizing away redundant states
• iodevice.vhd - The I/O device that translates numbers to hexadecimal output on the 7-seg LEDs.
• ram32x8.vhd - The program RAM implemented with the lpm_ram megafunction.
• rom32x10.vhd - The program ROM implemented with the lpm_rom megafunction.
• ssc_system.gdf - The toplevel design file including the core, memories, and iodevice.
• ssc_system.scf - The simulation file for the toplevel design.
• program0.ssc - A simple program that tests basic load and store operations, and jumps.
• program0.mif - Assembled lpm MIF file of above assembly program.

• bustri.vhd
• bustri_inst.vhd
• bustribi.vhd
• bustribi_inst.vhd
• input_test.vhd
• iodevice.vhd
• iodevice2.vhd
• ram32x8.vhd
• ram8x8_secondary.vhd
• rom32x10.vhd
• slowclock.vhd
• ssc_core.vhd
• io_sys.gdf
• test_main.gdf
• test_secondary.gdf

Below is a sample implementation of a tri-state buffer design from the Altera website,.

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY bidir IS
    PORT(
        bidir   : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0);
        oe, clk : IN STD_LOGIC;
        inp     : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
        outp    : OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
END bidir;

ARCHITECTURE maxpld OF bidir IS
SIGNAL  a  : STD_LOGIC_VECTOR (7 DOWNTO 0);  -- DFF that stores 
                                             -- value from input.
SIGNAL  b  : STD_LOGIC_VECTOR (7 DOWNTO 0);  -- DFF that stores 
BEGIN                                        -- feedback value.
    PROCESS(clk)
    BEGIN
    IF clk = '1' AND clk'EVENT THEN  -- Creates the flipflops
        a <= inp;                    
        outp <= b;                  
        END IF;
    END PROCESS;    
    PROCESS (oe, bidir)          -- Behavioral representation 
        BEGIN                    -- of tri-states.
        IF( oe = '0') THEN
            bidir <= "ZZZZZZZZ";
            b <= bidir;
        ELSE
            bidir <= a; 
            b <= bidir;
        END IF;
    END PROCESS;
END maxpld;

Sample Programs and Simulation Results

Description - The following assembly language program saves a few values into the data memory, loads the value 0, increments it, decrements it, and then proceeds to simply reload the values it saved into data memory before starting over. The Altera simulation results for running this program (after assembling it into machine instructions) follow.

L1:	load 1
	sto 0
	load 2
	sto 1
	load 3
	sto 2
	load 0
	inc
	dec
	lea 0
	lea 1
	lea 2
	j L1

Discussion of Simulation Results - The above simulation results for the SSC running the simple load/store test program outlined above confirm that the processor correctly executes the instructions. The yellow highlighted register shows the instruction register (IR)'s value as a function of time. The gray highlighted register shows the accumulator's (ACC) values. The brown highlights emphasize any write enables to data memory. The reddish lines denote when a new instruction is loaded into the instruction register, and the blue lines show on which clock cycle the program counter (PC) is updated at the end of each instruction.

The time difference between a blue line forward to the next red line show how many clock cycles are required to fetch and load a new instruction from the program memory. In each case, two clock cycles are needed after the program counter changes before the new instruction is loaded. The time need to execute one instruction can be obtained from the time difference between two red lines. The number of clock cycles required to actually execute each instruction varies with the type of instruction. For example, a STORE (sto) instructions take more clock cycles than an increment instruction since it must set the address and data, and then set the memory write enable signal high. The execution characteristics of each different type of instruction can be thus verified in the simulation.

An instruction-by-instruction description follows.

• c0 - The instruction 0x201 ( load 1 ) is loaded. Note that on the next rising edge, the accumulator receives the value 1.
• c1 - The instruction 0x020 ( sto 0 ) is loaded. The value of the accumulator is applied to the data memory write lines, as well as the address 0 data memory address lines. The write enable goes high on the next clock cycle, and the data in the ACC is written to memory.
• c2 - The instruction 0x202 ( load 2 ) is loaded. Note that on the next rising edge, the accumulator receives the value 2.
• c3 - The instruction 0x021 ( sto 1 ) is loaded. The value of the accumulator is applied to the data memory write lines, as well as the address 1 data memory address lines. The write enable goes high on the next clock cycle, and the data in the ACC is written to memory.
• c4 - The instruction 0x203 ( load 3 ) is loaded. Note that on the next rising edge, the accumulator receives the value 3.
• c5 - The instruction 0x022 ( sto 2 ) is loaded. The value of the accumulator is applied to the data memory write lines, as well as the address 2 data memory address lines. The write enable goes high on the next clock cycle, and the data in the ACC is written to memory.
• c6 - The instruction 0x200 ( load 0 ) is loaded. Note that on the next rising edge, the accumulator receives the value 0.
• c7 - The instruction 0x320 ( inc ) is loaded. On the next rising edge, the accumulator's value is incremented to 1.
• c8 - The instruction 0x340 ( dec ) is loaded. On the next rising edge, the accumulator's value is decremented back to 0.
• c9 - The instruction 0x000 ( lea 0 ) is loaded. The memory address 0 is applied to the data memory's address lines, and on the next clock the value of the data memory at location 0 is loaded into the accumulator. Note that this is the value that was stored in instruction c1
• c10 - The instruction 0x001 ( lea 1 ) is loaded. The memory address 1 is applied to the data memory's address lines, and on the next clock the value of the data memory at location 1 is loaded into the accumulator. Note that this is the value that was stored in instruction c3

SSC Assembler Information and Source Codes

Assembly Language Description - The SSC assembler provides a quick and easy way to write assembly programs for either the standard original SSC implementations, or with the parallel extensions. The assembler provides some basic error checking, and allows for jumps to mnemonic labels in the source file. A jump command with an argument that begins with an alphabetic character indicates a logical jump to a labeled instruction, while a numeric argument specifies a hard address. Labels must be on a line with an instruction, and must begin with an alphabetic character. Labels cannot have spaces in them and must end directly with a colon ':'. All numeric values must be specified in decimal format (base 10). The values will be converted to the binary 1's and 0's equivalent for the machine instructions. Comments in the assembly begin with a semicolon ';' and extend to the end of the line.

Mnemonic	Argument	Legal values
load	IMMEDIATE	8-bit value (-127 - 126)
lea	ADDRESS	5-bit addr (0 - 31)
sto	ADDRESS	5-bit addr (0 - 31)
j	LABEL or ADDRESS	5-bit addr (0 - 31)
jmq	LABEL or ADDRESS	5-bit addr (0 - 31)
jc	LABEL or ADDRESS	5-bit addr (0 - 31)
jo	LABEL or ADDRESS	5-bit addr (0 - 31)
add	OPERAND ADDRESS	5-bit operand addr (0 - 31)
and	OPERAND ADDRESS	5-bit operand addr (0 - 31)
outb
outbpb	REGISTER ADDRESS	3-bit data buffer (0-7)
sdpcpu
inb
wdpcpu
inc
dec
lsh
rsh
inv
swap
leamq

The output of the assembler is a 32x8 sized MIF file that can be loaded directly into the program memory of the SSC using the standard Altera lpm_rom LPM_FILE parameter.

To invoke the assembler on a source file:

C:\› sscasm.exe program0.ssc program0.mif

• sscasm.cpp - The C++ source code for the assembler program.
• sscasm.exe - A pre-compiled Win32 assembler executable.

Acknowledgements

The lab handout was provided by Professor Maxwell. Professor Maxwell also oversaw the lab and our progress. All questions were directed to Professor Maxwell.
The original lab assignment can be found here.