A 200kHz Ė 2MHz Analog Spectrum Analyzer
Aron Dobos, Tyler Strombom
11 December 2004
II. Introduction and Theory
III. Circuit Design
††††††††††† Design Overview
††††††††††† a. Sweep Generator
††††††††††† b. Voltage Controlled Oscillator
††††††††††† c. Multiplier
††††††††††† d. Resolution Filter
††††††††††† e. Output Rectifier and Amplifier
††††††††††† f. Power Supply
IV. Testing, Difficulties, and Results
A 200 kHz Ė 2 MHz analog spectrum analyzer was built and tested in the Hicks Laboratory.† After developing the specifications for each of the analyzer components, the circuit was constructed on a breadboard and tested with various inputs.† Pure sinusoidal and square pulse signals were both tested to confirm the correct functioning of the circuit. Spectrum graphs were generated for known input frequencies, and the instrument was thereby calibrated.† The results obtained confirmed the applicability of Fourier and modulation theory to the design of analog spectrum analyzers.
When two sinusoids are multiplied in the time domain, the result is a frequency shift in the frequency domain.
If the two sinusoids are of the same frequency, then the result in the frequency domain is a 0 Hz D.C. value. Our spectrum analyzer assumes that the input signal is a sum of sinusoids and therefore, has multiple frequencies. By multiplying the input signal by a sinusoid of varying frequency, D.C. signals are created when the varying sinusoid is of the same frequency as one of the input signalís frequencies.
To create the varying sinusoid, a variable sweep generator and a voltage controlled oscillator were used. The variable sweep generator outputs a voltage that repeatedly increases between two voltages over a time period. The result is a saw-tooth waveform. This is then the input for the voltage controlled oscillator. As the input voltage increases, the sinusoidal output of the VCO increases in frequency. We now have a varying sinusoid.
The varying sinusoid and the signal that will be analyzed are then multiplied by an analog multiplier. A fourth order Butterworth filter was then used to filter out the resulting DC signals.† The resolution bandwidth of the filter is determined by considering the sweep time and the desired frequency range.† Some of the theoretical spectrumís detail is inevitably lost due to the finite frequency width of the filter.† As the resolution filter gets narrower, the ideal and actual spectral representations of the input signal begin to match, until the filter is of zero bandwidth and in effect is a impulse form.† The transformation of the ideal spectrum into the displayed representation is simply a convolution.† If too narrow a passband is chosen for the filter, the output spectrum will be distorted because the sweeping signal does not stay at a specific frequency long enough for the filter to accurately discern the signal shape.† A solution is to simply increase the sweep time until an undistorted spectrum is achieved, but this is not truly a viable solution.† Spectrum analyzer theory gives an equation for the optimum resolution filter bandwidth. Given a sweep time T, and frequency span S, the filter bandwidth is
Given a span from 200kHz to 2 MHz, and a sweep time of 1/30 s, the resolution bandwidth for the spectrum analyzer is calculated to be approximately 4.8kHz.
The spectrum analyzer circuit is designed around readily available integrated circuits to perform signal generation, amplification, modulation, and filtration.† The function generator IC used in the sweep and VCO is the Maxim MAX038.† The opamp used throughout the circuit was the LM411 JFET opamp instead of the standard 741 simply because of availability in the laboratory.† The Analog Devices AD734 implemented the multiplier component.† The resolution filter was a 4th-order Butterworth design built from two LM411-based second-order sections.† All diodes pictured were of type 1N4002, and most resistors were 1/4W with 5% tolerance.† In places were voltage levels required precise specification, 1% metal film resistors were used.† In places were IC supplies were bypassed to ground, 0.47 uF ceramic disc capacitors were used.† All the parts are low-cost and readily available.† An Hewlett Packard HP1222A 10MHz oscilloscope was used for the CRT X-Y-Z display functionality. The spectrum analyzer was built from such "building blocks" instead of designing the function generators and multipliers from scratch for performance reasons, time constraints, and to allow the designers to focus more on a solid foundation of the theoretical aspects of the analog spectrum analyzer.† An in depth discussion of each of the subcircuits follows.
a. Sweep Generator
The sweep generator is based on the MAX038 function generator IC configured to produce a 10% duty cycle triangle wave.† The CRT X-axis voltage output is a zero centered 4 V p-p signal that also drives a Schmitt-trigger based Z-axis blanking circuit.† The x-axis output signal is passed through a precision DC restorer to obtain a 0-4 V ramp suitable for controlling the VCO.† Ceramic bypass capacitors valued at 0.47 uF stabilize the supply voltage, and are placed in close proximity to the IC for maximum effect.† To achieve an accurate duty cycle configuration voltage and the oscillation frequency, 1% resistors are used.
Sweep:† Opamp U2 in conjunction with resistors R1 and R3 establish a stable reference voltage of 2.29 V on the DADJ pin of the MAX038 to set the duty cycle at approximately 10%.† Refer to the MAX038 data sheet for more specific configuration information.† The 2.50 V reference voltage is used to establish a stable bias current through Rin into IIN to set the frequency in conjunction with Cf.† Given a desired sweep time of 1/30 second, a frequency of 30Hz is set by choosing a suitable large 10 uF for Cf appropriate for the low frequency.† The appropriate Rin is then calculated given the relationship
resulting in approximately 8.66 k, using 1% resistors.† Having set the sweep frequency, the function generator is configured with pins A0 and A1 to produce a triangular wave.† Since the MAX038 output is defined as 2V p-p, a non-inverting gain of 2 is obtained with U3, R8, and R10.† The expected 100Ω load is simulated with R2, and is necessary since ideally no current flows into the opamp U3.†† Initial testing of the sweep circuitry showed high frequency glitches at the zero volt crossing on the output ramp from the MAX038.† The glitch is clearly observable in the oscilloscope output shown below:
The glitch was minimized by simply adding a 0.47 uF capacitor C5 in parallel with the 100Ω load resistor to filter out the zero-crossing noise.† The fixed signal is shown below.† Note the actual sweep frequency of 28.91Hz.† It is unclear why the previous scope screen showed a clearly incorrect frequency.
This is the CRT x-axis voltage signal.† It is now sent through a precision D.C. restorer formed by C4, R11, U4, and the two diodes.† The anode of the lower diode is pulled to +Vcc through R11, permanently forward biasing it with some small bias current, and thus setting the anode at +0.7 volts (assuming a constant drop model).† Therefore, the upper diode will be forward biased when the voltage is less than zero, charging capacitor C4 up to a voltage equal to the most negative value seen on the input.† As such, the voltage at the positive terminal of the unity gain buffer formed by U4 will be a D.C. restored signal from 0 to 4 volts, suitable for driving the VCO frequency control input current.† The restored voltage signal is shown below:
To control the Z-axis or blanking signal, a square 5V pulse is required with appropriate timing to clear the CRT upon retrace.† The blanking circuit is a basic 0-volt centered Schmitt trigger bistable consisting of U5 and the threshold setting resistors R5, R12, R4, and R7.† The open collector output of U5 is pulled to Vcc through R6.† The output voltage is divided equally by R5 and R12 for input into the unity gain buffer U8.† This voids any need for rail-to-rail opamps since the voltage levels at the U8 input are half of the supply rails.† R5 and R12 are purposefully chosen to be very large compared to R6 to allow only a minimum of current to flow through them, keeping the comparator output as close to +Vcc as possible.† The output of U8 is fed back through the resistor network R4 and R7 to set the threshold voltage.† U6 is another unity gain buffer required to keep the input terminal characteristics of the logic inverter U7A from modifying the output voltage of U8.† It was discovered in the lab that this was necessary, since the negative voltage swing of U8 was limited to some value greater than -Vcc without the U6 buffer.† The open collector voltage is pulled to Vcc by R9, and forms the square pulse for the CRT z-axis blanking.† When the comparator output is high, the threshold voltage at V+ of the comparator is positive and determined by R4 and R7.† When the threshold is crossed by the sweep ramp, the comparator flips and the output voltage is tied to -Vcc, causing the threshold voltage V≠+ to go negative, but with the same magnitude as before.† This defines the threshold levels centered about ground, which is appropriate considering that the sweep input is zero centered.
b. Voltage Controlled Oscillator
The voltage controlled oscillator (VCO) generates a sinusoidal signal whose frequency is proportional to the input voltage.† The input is a 0-4 V ramp from the sweep generator, and the output is a 2 V p-p sinusoid varying from approximately 250 kHz to slightly above 2 MHz.† Opamps U4 and U5 form a precision duty cycle adjustment circuit for trimming the duty cycle of the sine wave to exact 50%.† Any deviation from a 50% duty cycle will cause some even harmonics to appear in the output, which when modulated with the test signal will result in spikes on the frequency spectrum where in actuality none exist.† To save time in the lab, the duty cycle circuit was not actually built, and the DADJ pin was simply grounded.† According to the MAX038 datasheet, 1-2% deviation form 50% is thus to be expected.† The schematic is included below.
Because IIN on the MAX038 must always be biased with a positive current,† a small D.C. offset is added to the input signal by the non-inverting summation circuit formed by R4, R5, R6, R7, R8, and U3.†† The stable 2.50 V reference voltage provided by the MAX038 on the Vref pin is injects current through R6 at the node of the U3's positive terminal.† By superposition it can be shown that this configuration will result in 0.25 V at V+, giving a D.C. offset of 0.5 V at the output of U3 because of the non-inverting gain of 2.† The 0-4 V input signal is also scaled by the resistors R5, R4, and R6, resulting in a final ramp output from 0.5V - 4.5V.† This voltage across R9 establishes the frequency control bias current into IIN.
Initial testing revealed that a standard LM411 opamp would not suffice for U3 because of the need to reach 4.5 volts or higher given 5V supply rails.† The TLV2772 rail-to-rail opamp was chosen, and resulted in a very clean VCO ramp. The signal is shown clearly in the oscilloscope screen below.
The oscillation frequency of the VCO is configured by IIN and CF as before in the sweep circuit.† In the laboratory, CF was chosen to be 220 pF from the available capacitors.† Given the ramp minimum at 4.56-4.16 = 0.4 V,† 10k Ω for R9, and 220 pF, the low frequency of 0.182 MHz, or 182 kHz.† Likewise the maximum VCO frequency is calculated to be 2.07 MHz.† These calculations indicate the frequency range detected by the spectrum analyzer.† A snapshot of the VCO output signal is included below.† Note that due the continually sweeping frequency, the oscilloscope does not properly trigger.
In the schematic the MAX038 output is buffered by a unity gain configuration of U2, but in practice it was unnecessary to include this circuit, and thus the input for the multiplier circuit is taken directly from the MAX038.
The multiplier was constructed using an AD734 chip with the following connection diagram
The chipís transfer function of (XY)/U where X and Y are the input functions and U is the denominator determined by the denominator interface. The basic multiplier circuit is shown below
The internal denominator of the chip is 10 V. Because we wish to have as little distortion of the multiplied signal as possible, we want the denominator to be as close to 1 V as possible. To set up nonstandard denominator values, the data sheet provides the following configuration
The data sheet also provides a table suggesting values for R1 and R2 to set nonstandard denominator values. For a denominator of 1V, R1=174 kΩ and R2 = 620 kΩ. Using the resistor components available in the lab, R1 was approximated with a 180 kΩ resistor and R2 was approximated with a 680 kΩ resistor. The final circuit is shown below
d. Resolution Filter
The fourth order low pass Butterworth filter was designed by cascading two second order sections† using an L411 op amp of the following design:
Summing the currents and finding V1:
Solving for the transfer function:
The transfer function of a second order low pass Butterworth filter is of the form:
For a cutoff frequency at 4.8 kHz,† =2π*4.8*1000. Setting R1=R2=1 kΩ,
We also can solve for Q
Cascading the two second order filters, we have
According to the Butterworth Low Pass Filter table, for a fourth order filter the two values for Q are .541 and 1.306.† Knowing Q, we can solve for the ratio of C1 to C2 and C3 to C4.
With all resistors = 1 kΩ and multiple of the capacitors for each cascade equal to 1.099*10-15, we can solve for C1, C2, C3, & C4. For Q = .541, C1 = 35.88 nF and C2 = 30.64 nF. For Q = 1.306, C3 = 86.61 nF and C4 = 12.69 nF. Using the capacitors available in lab, C1 = 35.2 nF, C2 = 30.4 nF, C3 = 86.2 nF and C4 = 12.2 nF.
e. Output Rectifier and Amplifier
The output rectifier and amplifier circuit takes the absolute value of the output of the resolution filter since only the magnitude of the signal is desired on the spectrum display.† The circuit is simply an non-inverting amplifier with a gain of 11, whose output is rectified by the standard absolute value circuit based on the "superdiode".†† In the schematic shown below, U1 is the amplifier, and the combination of U2 and U3 form the rectifier.
f. Regulated Power Supply
To achieve a very clean +/- 5 V power supply, the internal breadboard supply was configured for approximately +/- 7 V, and then trimmed to +/- 5V by the straightforward circuit shown below.
Bypass capacitors C3 and C6 are chosen to be ceramic disc types, and the remaining C1, C2, C4, and C5 are electrolytic to give the capability of large current drains.
Testing, Difficulties, and Results
A function generator was used to generate various input signals to test the spectrum analyzer's ability to display the frequency spectrum of the input.† Sine waves of frequencies between 200kHz and 2MHz were used to tested the response range and the resolution bandwidth of the spectrum analyzer.
The circuit was first constructed without the Z-axis blanking bistable circuit, and without the output rectifier.† This meant that the negative peaks were shown also, an that the CRT retrace was not removed from the display.† Disturbances were observed around the peaks of spectrum, shown below for a sine wave input.
Since the sweep is a 10% duty cycle triangle wave, the return sweep is much faster than the forward sweep.† This causes the VCO to ramp down much faster on the return trace.† Likely the resolution filter does not correctly filter at the return rate, resulting in the medium size distortion before the clean peak.† Implementing the Z-axis blanking circuit disables the electron beam on the retrace, so the distortions are not shown. Connecting the sweep and spectrum outputs to an oscilloscope, the problem, and its solution, are clearly observable.
After constructing the Z-axis blanking pulse generator and the output rectifier, a series of tests were run confirming the correct functioning of the spectrum analyzer.† Only the parts of the output signal between the Z-axis pulses are shown on the CRT, resulting in the graphs shown below.
Test 1.† The frequency spectrum of a square pulse train with a fundamental frequency of about 350kHz is shown.† Notice that the harmonics of decreasing magnitude are cleanly displayed at even spacing.
Test 2. A pure sine wave at approximately 350 kHz is shown.† The spectrum analyzer cleanly displays the single frequency present in the input.
Test 3. A pure sine wave at approximately 1 MHz is shown.† As before, the spectrum analyzer cleanly displays the single frequency present in the input.
Test 4. A pure sine wave at approximately 1.8 MHz is shown.† Just as before, the spectrum analyzer cleanly displays the single frequency present in the input.
The simple testing procedures confirm the correct functioning of the spectrum analyzer circuit.† Due to time constraints, further testing and calibration was set aside.
One remaining difficulty with the current implementation of the spectrum analyzer is the visible fluctuation of the height of the spectral peaks.† One possible reason for this seemingly random instability is that the initial phase angle of the VCO at the start of the sweep is not synchronized to be the same on each sweep.† As a result, when the VCO signal is multiplied by a constant phase test signal, there will be fluctuations in the mean value of the resulting signal when both are at equal frequencies.†
Solving the problem could involve forcing the input and the VCO to be phase matched.† Circuitry that would lock the VCO's phase to the test signal at the start of the sweep would ensure that mean value of matched frequencies would be consistent, thereby removing the visible fluctuations.† This could implemented by shutting down the sweep after retrace, waiting for a predefined phase front on the input, and at that moment restart the sweep with the VCO at an equal phase.†