Engineering 15 Lab 2
Brian Park, Alex Benn, Aron Dobos
28 September 2005
Abstract
A 4 bit addition and subtraction unit was implemented in VHDL. The design was hierarchical, and was based on smaller building blocks like the half adder and full adder circuits that were independently tested. The final arithmetic unit was programmed onto the Altera Flex10K device, providing a two digit hexadecimal 2’s complement display as well as inputs for the two numbers. Testing showed that the device indeed worked as expected.
Simulations
The half adder circuit was tested using the MAXPLUS-II simulator. The results are shown in Figure 1.
Figure 1. Half adder simulation
A non-exhaustive simulation was run also for the four bit adder. The results are shown in Figure 2.
Figure 2. 4 Bit Adder simulation.
The hexadecimal decoder was tested directly on the Altera board without prior simulation. The display worked properly as seen below in the testing procedures for the arithmetic unit.
Flex10K Testing
The arithmetic unit was downloaded onto the Flex10K chip and wired to drive the 2 segment LCD display and take input from the 8-pin (2 four bit numbers) switch block. The photographs included below demonstrate the correct functioning of the circuit. Switches 1-4 provided the input X(3..0), and switches 5-8 Y(3..0). When the pushbutton PB_1 was pressed, addition was performed, otherwise subtraction. The functions implemented were
X + Y = Z (PB_1 pressed)
-X + Y = Z (PB_1 released)
When performing subtraction, only the output is represented as two’s complement. The inputs are still considered as unsigned integers.
Figure 3. - 0111 + 0010 = 0xb (1001+0010=0xb; -7 + 2 = -5)
Figure 4. 0111 + 0010 = 0x9 ( 7+2=9 )
Figure 5. – 1011 + 1010 = 0xf ( 0101+ 1010 = 0xf; -11 +10 = -1 )
Figure 6. 1011 + 1010 = 0x15 ( 11 + 10 = 21 )
VHDL Code
A complete listing of the VHDL code files is included below.
halfadd.vhd – Half adder circuit
fulladd.vhd – Full adder circuit
adder4.vhd
– Four bit adder with Carry in/out
disp7seg.vhd
– 7 segment display decoder with 5 bit input
task5.vhd
– Adds two four bit numbers and displays result
task6extra.vhd – Adds or subtracts two four bit numbers and displays result in 2’s complement
halfadd.vhd
-- e15 lab 2
-- alex benn,
brian park, aron dobos
--
21 sept 2005
-- half adder circuit
library ieee;
use
ieee.std_logic_1164.all;
use
ieee.std_logic_arith.all;
entity halfadd is
port (
A,
B : in std_logic;
S, C : out std_logic
);
end
halfadd;
architecture arch1 of halfadd is
begin
S
<= A xor B;
C
<= A and B;
end
arch1;
fulladd.vhd
-- e15 lab 2
-- alex benn,
brian park, aron dobos
-- 21 sept 2005
-- fulladd :
full adder circuit implemented with two half adders
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity fulladd is
port (
Cin, x, y : in std_logic;
S, Cout : out std_logic
);
end fulladd;
architecture arch1 of fulladd
is
signal Si, Ci1, Ci2: std_logic;
COMPONENT halfadd
port (
A,
B : in std_logic;
S, C : out std_logic
);
END COMPONENT;
begin
ha1 : halfadd port map (x, y, Si, Ci1);
ha2 : halfadd port map (Si, Cin, S, Ci2);
Cout <= Ci1 or Ci2;
end arch1;
adder4.vhd
-- e15 lab 2
-- alex benn,
brian park, aron dobos
-- 21 sept 2005
-- adder5:
implements a 4 bit ripple adder with carry in/out
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity adder4 is
port ( Cin : in std_logic;
X,Y : in std_logic_vector(3 downto 0);
s : out std_logic_vector(3 downto 0);
Cout : out std_logic
);
end adder4;
architecture arch1 of adder4 is
signal C: std_logic_vector(1 to 3);
component fulladd
port (
Cin, x, y : in std_logic;
S, Cout : out std_logic
);
end component;
begin
-- instantiate
the ripple adder components
stage0 : fulladd port map (Cin, X(0), Y(0), S(0), C(1) );
stage1 : fulladd port map (C(1), X(1), Y(1), S(1), C(2) );
stage2 : fulladd port map (C(2), X(2), Y(2), S(2), C(3) );
stage3 : fulladd port map (
x => X(3), y => Y(3), Cin => C(3), s => S(3), Cout
=> Cout);
end arch1;
disp7seg.vhd
-- e15 lab 2
-- alex
benn, brian park, aron dobos
-- 21 sept 2005
-- disp7seg: decodes a 5 bit binary number into a 2
digit hexadecimal display
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity disp7seg is
port ( data : in std_logic_vector(4
downto 0);
digit0 : out std_logic_vector (6 downto 0);
digit1 : out std_logic_vector (6 downto 0) );
end disp7seg;
-- 5 bits to 2 7segment hex
------------------------------------------
-- converts a 5 bit value into the correct
-- signal pattern for the 7
segment displays
-- the 7 bit return value
is the output
-- for segments in the
following order: gfedcba
-- or bits 6543210
-- Note: the LEDs on the Altera board are active-low.
--
-- - a
- - 0 -
-- f b 5
1
-- - g
- <=> - 6 -
-- e c 4
2
-- - d
- - 3 -
architecture
arch1 of disp7seg is
begin
process( data(3 downto 0) )
begin
case data(3 downto 0) is
when "0000" =>
digit0
<= "1000000";
when "0001" =>
digit0
<= "1111001";
when "0010" =>
digit0
<= "0100100";
when "0011" =>
digit0
<= "0110000";
when "0100" =>
digit0
<= "0011001";
when "0101" =>
digit0
<= "0010010";
when "0110" =>
digit0
<= "0000010";
when "0111" =>
digit0
<= "1111000";
when "1000" =>
digit0
<= "0000000";
when "1001" =>
digit0
<= "0010000";
when "1010" =>
digit0
<= "0100011";
when "1011" =>
digit0
<= "0000011";
when "1100" =>
digit0
<= "0100111";
when "1101" =>
digit0
<= "0100001";
when "1110" =>
digit0
<= "0000100";
when others =>
digit0
<= "0001110";
end case;
end process;
digit1 <= "1111001" when data(4) = '1' else "1000000";
end arch1;
task5.vhd
-- e15 lab 2
-- alex benn,
brian park, aron dobos
-- 21 sept 2005
-- task 5: implements a 4 bit adder with hexadecimal display
capability
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity task5 is
port (
X, Y : in std_logic_vector(3 downto 0);
D0, D1 : out std_logic_vector( 6 downto 0)
);
end task5;
architecture arch1 of task5 is
-- declare
the components we are going to use
component adder4 is
port ( Cin : in std_logic;
X,Y : in std_logic_vector(3 downto 0);
s : out std_logic_vector(3 downto 0);
Cout : out std_logic
);
end component ;
component disp7seg is
port ( data : in std_logic_vector(4 downto 0);
digit0 : out std_logic_vector
(6 downto 0);
digit1 : out std_logic_vector
(6 downto 0) );
end component;
signal addresult : std_logic_vector(4 downto 0); -- 5 bit register to hold result of addition
signal gnd : std_logic; -- used to tie
the carry in to the adder to ground
begin
gnd
<= '0';
-- instantiate
the adder
adder : adder4
port map ( gnd,
X, Y, s => addresult(3 downto
0), Cout => addresult(4)
);
-- instantiate
the 7 segment led display decoder
decoder :
disp7seg port map( data => addresult, digit0 =>
D0, digit1 => D1 );
end arch1;
task6extra.vhd
-- e15 lab 2
-- alex benn,
brian park, aron dobos
-- 21 sept 2005
--
task6_extra: implements addition and subtraction
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity task6extra is
port (
addsub : in std_logic;
X, Y : in std_logic_vector(3 downto 0);
D0, D1 : out std_logic_vector( 6 downto 0)
);
end task6extra;
architecture arch1 of task6extra is
component adder4 is
port ( Cin : in std_logic;
X,Y : in std_logic_vector(3 downto 0);
s : out std_logic_vector(3 downto 0);
Cout : out std_logic
);
end component;
component disp7seg is
port ( data : in std_logic_vector(4 downto 0);
digit0 : out std_logic_vector
(6 downto 0);
digit1 : out std_logic_vector
(6 downto 0) );
end component;
signal negx2cmp :
std_logic_vector(3 downto
0);
signal gnd, cout : std_logic;
signal addresult : std_logic_vector(4 downto 0);
signal subresult : std_logic_vector(4 downto 0);
signal decodein : std_logic_vector(4 downto 0);
begin
gnd
<= '0';
-- obtain 2's
complement representation of -X
comp2 : adder4
port map(gnd, not(X), "0001", negx2cmp, cout);
-- perform subresult
<= -X + Y
subtractor : adder4 port map(gnd, negx2cmp,
Y, subresult(3 downto 0), subresult(4) );
-- perform addresult
<= X + Y
adder : adder4
port map(gnd, X, Y, addresult(3
downto 0), addresult(4) );
-- select the output based on addsub
decodein
<= addresult when addsub
= '0' else subresult;
decoder :
disp7seg port map (decodein, D0, D1);
end arch1;